Synchronous circuits often employ some form of clock switching circuitry to select from among two or more clock signals. For example, some complex systems include multiple subsystems timed to different clock signals. Programmable logic devices that support such locally synchronous, globally asynchronous systems include clock control circuitry capable of routing different clock signals to different subsystems. Similar control circuitry may also support circuits capable of operating in response to two or more separate clock signals. For example, integrated circuits that operate in accordance with the proposed PCI-X bus interface standard operate in response to either a 133 MHz clock signal or a 66 MHz clock signal.
FIG. 1 (prior art) depicts a two-to-one clock control circuit 100 that provides either of two clock signals CLK1 and CLK2 on a clock-distribution node CLK3, and advantageously switches between those two clock signals without generating a glitch on node CLK3. (As with other designations herein, CLK1, CLK2, and CLK3 each refer both to a signal and its corresponding node; whether a given designation refers to a signal or a node will be clear from the context.)
Clock control circuit 100 includes NAND gates 101-103, D-type flip-flops 111 and 112, 2-to-1 multiplexers 121 and 122, a configuration memory cell 123, inverters 131-134, and n-channel pass transistors 141 and 142. Inverter 134 and NAND gate 103 are connected to form keeper circuit 150.
Clock signal CLK1 is applied to inverting and non-inverting input terminals of multiplexer 121. Multiplexer 121 is controlled by a configuration value stored in configuration memory cell 123. Thus, if configuration memory cell 123 stores a logic “0” value, then multiplexer 121 routes the inverse of clock signal CLK1 (i.e., CLK1b). Conversely, if configuration memory cell 123 stores a logic “1”, value, then multiplexer 121 routes the clock signal CLK1. The output terminal of multiplexer 121 is coupled to the clock input terminal of flip-flop 111. In the described embodiment, flip-flop 111 is a rising edge triggered flip-flop. As described below, multiplexer 121 effectively enables flip-flop 111 to be triggered by either the rising edges or the falling edges of the CLK1 signal.
A secondary clock signal CLK2 is applied to inverting and non-inverting input terminals of multiplexer 122. Multiplexer 122 is also controlled by a configuration value stored in configuration memory cell 123. Thus, if configuration memory cell 123 stores a logic “0” value, then multiplexer 122 routes the inverse of clock signal CLK2 (i.e., CLK2b). Conversely, if configuration memory cell 123 stores a logic “1” value, then multiplexer 122 routes the clock signal CLK2. The output terminal of multiplexer 122 is coupled to the clock input terminal of flip-flop 112. In the described embodiment, flip-flop 112 is a rising edge triggered flip-flop. As described in more detail below, multiplexer 122 effectively enables flip-flop 112 to be triggered by either the rising edges or the falling edges of the CLK2 signal.
A clock select signal SEL is provided to an input terminal of NAND gate 101. The Q output terminal of flip-flop 112, which carries output signal Q112, is coupled to the other input terminal of NAND gate 101. The clock select signal SEL is also provided to inverter 133. In response, inverter 133 provides the inverse of the clock select signal SEL to an input terminal of NAND gate 102. The Q output terminal of flip-flop 111, which carries output signal Q111, is coupled to the other input terminal of NAND gate 102.
NAND gate 101 provides input signal D111, to the D input terminal of flip-flop 111. NAND gate 102 provides input signal D112 to the D input terminal of flip-flop 112. Flip-flop 111 has a reset input terminal (R) coupled to receive a power-on-reset signal POR. Flip-flop 112 has a set input terminal (S) coupled to receive the power-on-reset signal POR.
The output terminals of flip-flops 111 and 112 are further connected to input terminals of inverters 131 and 132, respectively. The output terminals of inverters 131 and 132 are coupled to gate electrodes of pass transistors 141 and 142, respectively. The CLK1 and CLK2 signals are provided to the drain terminals of pass transistors 141 and 142, respectively. The source terminals of pass transistors 141 and 142 are commonly connected to node N1. The signal on node N1 is provided as the output clock signal CLK3.
Node N1 is further coupled to an input terminal of NAND gate 103. The other input terminal of NAND gate 103 is coupled to receive the inverse of the POR signal (i.e., PORb). The output terminal of NAND gate 103 is connected to the input terminal of inverter 134. The output terminal of inverter 134 is connected to node N1. When the PORb signal has a logic high value, NAND gate 103 is configured as an inverter. Under these conditions, NAND gate 103 and inverter 134 form a keeper circuit that is capable of holding the state of the signal on node N1. Note that inverter 134 and NAND gate 103 are designed to be weak relative to pass transistors 141 and 142. As a result, when clock signals CLK1 and CLK2 are driven onto node N1, these clock signals can easily change the state of node N1. For a more detailed description of clock control circuit 100, see U.S. Pat. No. 6,472,909 to Steven P. Young, issued Oct. 29, 2002, which is incorporated herein by reference.
Clock control circuit 100 works well in many applications, but has two potential shortcomings. First, switching between clocks requires each of flip-flops 111 and 112 to change state, which in turn requires each flip-flop 111 and 112 to be clocked by respective clock signals CLK1 and CLK2. Clock control circuit 100 is therefore incapable of switching between clock sources unless both clock sources are producing edges. If, for example, clock signal CLK1 were to stop, control circuit 100 would be unable to switch to clock signal CLK2. Second, control circuit could produce a “runt” pulse if a select-signal transition arrives at one of the flip-flops coincident with the respective clock signal, so select signal SEL should be timed to meet the set-up and hold-time requirements of the flip-flops. There is therefore a need for a glitchless clock control circuit that is capable of switching away from a failed clock, and for which there is no set-up or hold time requirement for the select signal.